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[Author] Jun HA(30hit)

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  • The IPv6 Software Platform for BSD

    Tatuya JINMEI  Kazuhiko YAMAMOTO  Jun-ichiro itojun HAGINO  Shoichi SAKANE  Hiroshi ESAKI  Jun MURAI  

     
    INVITED PAPER

      Vol:
    E86-B No:2
      Page(s):
    464-471

    IPv6 is designed to solve the exhaustion of the address space, which are one of the biggest problems in the current Internet. The WIDE project has been involved in IPv6 since its early stage, and organized the KAME project in 1998 in order to accelerate its deployment. The KAME project has provided a free, specification-compliant implementation of IPv6 on BSD variants. With its quality and the continuous efforts on it, the implementation has established the position of a reference to IPv6, and has been adopted in BSD variants and in several commercial products. This paper first gives an overview of the IPv6 specifications, including its plug-and-play function, API, DNS, security and transition tools. It then describes the implementation by the KAME project. It is based on the BSD's original network stack, but explores some original enhancements for Neighbor Discovery or IPv6 addressing. Finally, it explains what is missing for the next steps of IPv6, concentrating on plug-and-play and security. The KAME project has joined, and will continue, the standardization and implementation efforts on the new issues.

  • A 17-Inch WXGA Full-Color OLED Display Using the Polymer Ink-Jet Technology

    Makoto SHIBUSAWA  Michiya KOBAYASHI  Jun HANARI  Kazuyuki SUNOHARA  Nobuki IBARAKI  

     
    PAPER-OLED Technology

      Vol:
    E86-C No:11
      Page(s):
    2269-2274

    We have developed a 17-inch WXGA full-color polymer OLED display by using newly developed ink-jet printing method. On the ink-jet technology, both droplet volume and landing position were precisely controlled pixel by pixel in order to get luminance uniformity. A pixel circuit having Vth variation-cancellation was adopted and the circuit was modified to realize high uniformity and high gray scale reproduction under the short horizontal period operation. Correction on gamma profile difference among RGB OLEDs was achieved by optimizing on configuration between integrated source driver circuit and outer reference voltage circuit in spite of using a common source driver IC having only one gamma profile. Peak control system, that is important for the large size and high luminance display, was utilized and improved image quality on human feeling and actual power consumption. With these efforts a uniform picture with 260,000 colors and wide viewing angle was achieved. It was proved that the ink-jet method was the optimal manufacturing technology for large-size and high-resolution OLED displays. And we found there is no singular problem on the large size OLED display utilized the ink-jet technology.

  • Design of LTCC Filters Using a Cross Patch

    Jun HAYASHI  Yoshio NIKAWA  

     
    PAPER-Passive(Filter)

      Vol:
    E86-C No:12
      Page(s):
    2412-2416

    A conventional waveguide filter is usually composed of a waveguide which is set with irises and posts inside. When dielectric material is not loaded inside the filter, the filter is too large to mount it on a planar circuit even if the frequency band is as high as the millimeter-wave band. In this paper, we propose a dielectric waveguide filter using LTCC (Low-Temperature Co-fired Ceramics) which can be mounted on a planar circuit. The dielectric waveguide filter using LTCC is composed of a dielectric-loaded waveguide including posts (via holes) and TEM-TE10 converters. The design method of the filter is shown and comparison of the simulated and the experimental results in the 6 GHz band is demonstrated. The simulated results agreed well with the experimental ones. To improve the attenuation characteristics, particularly at the above pass-band frequencies, an attenuation pole is added using a cross patch set inside the LTCC filter in the 25 GHz band. The effect of the cross patch is confirmed using the same simulation method as used for the 6 GHz band. As a result, it is confirmed that the cross patch is very useful for improving the attenuation characteristics at the above pass-band frequencies.

  • Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit

    Masashi KAMIYANAGI  Fumitaka IGA  Shoji IKEDA  Katsuya MIURA  Jun HAYAKAWA  Haruhiro HASEGAWA  Takahiro HANYU  Hideo OHNO  Tetsuo ENDOH  

     
    PAPER-Flash/Advanced Memory

      Vol:
    E93-C No:5
      Page(s):
    602-607

    In this paper, it is shown that our fabricated MTJ of 60180 nm2, which is connected to the MOSFET in series by 3 levels via and 3 levels metal line, can dynamically operate with the programming current driven by 0.14 µm CMOSFET. In our measurement of transient characteristic of fabricated MTJ, the pulse current, which is generated by the MOSFET with an applied pulse voltage of 1.5 V to its gate, injected to the fabricated MTJ connected to the MOSFET in series. By using the current measurement technique flowing in MTJ with sampling period of 10 nsec, for the first time, we succeeded in monitor that the transition speed of the resistance change of 60180 nm2 MTJ is less than 30 ns with its programming current of 500 µA and the resistance change of 1.2 kΩ.

  • Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits

    Fumitaka IGA  Masashi KAMIYANAGI  Shoji IKEDA  Katsuya MIURA  Jun HAYAKAWA  Haruhiro HASEGAWA  Takahiro HANYU  Hideo OHNO  Tetsuo ENDOH  

     
    PAPER-Flash/Advanced Memory

      Vol:
    E93-C No:5
      Page(s):
    608-613

    In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/ 1-poly Gate 0.14 µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60180 nm2 achieves a large change in resistance of 3.52 kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320 µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

  • A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm

    Weina ZHOU  Lin DAI  Yao ZOU  Xiaoyang ZENG  Jun HAN  

     
    PAPER-Application

      Vol:
    E95-D No:2
      Page(s):
    383-391

    Face detection has been an independent technology playing an important role in more and more fields, which makes it necessary and urgent to have its architecture reconfigurable to meet different demands on detection capabilities. This paper proposed a face detection architecture, which could be adjusted by the user according to the background, the sensor resolution, the detection accuracy and speed in different situations. This user adjustable mode makes the reconfiguration simple and efficient, and is especially suitable for portable mobile terminals whose working condition often changes frequently. In addition, this architecture could work as an accelerator to constitute a larger and more powerful system integrated with other functional modules. Experimental results show that the reconfiguration of the architecture is very reasonable in face detection and synthesized report also indicates its advantage on little consumption of area and power.

  • Bidirectional Packet Aggregation and Coding for Efficient VoIP Transmission in Wireless Multi-Hop Networks

    Jun HASEGAWA  Hiroyuki YOMO  Yoshihisa KONDO  Peter DAVIS  Katsumi SAKAKIBARA  Ryu MIURA  Sadao OBANA  

     
    PAPER

      Vol:
    E92-B No:10
      Page(s):
    3060-3070

    This paper proposes bidirectional packet aggregation and coding (BiPAC), a packet mixing technique which jointly applies packet aggregation and network coding in order to increase the number of supportable VoIP sessions in wireless multi-hop mesh networks. BiPAC applies network coding for aggregated VoIP packets by exploiting bidirectional nature of VoIP sessions, and largely reduces the required protocol overhead for transmitting short VoIP packets. We design BiPAC and related protocols so that the operations of aggregation and coding are well-integrated while satisfying the required quality of service by VoIP transmission, such as delay and packet loss rate. Our computer simulation results show that BiPAC can increase the number of supportable VoIP sessions maximum by around 87% as compared with the case when the packet aggregation alone is used, and 600% in comparison to the transmission without aggregation/coding. We also implement BiPAC in a wireless testbed, and run experiments in an actual indoor environment. Our experimental results show that BiPAC is a practical and efficient forwarding method, which can be implemented into the current mesh hardware and network stack.

  • Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS

    Pengjun WANG  Yuejun ZHANG  Jun HAN  Zhiyi YU  Yibo FAN  Zhang ZHANG  

     
    PAPER-Cryptography and Information Security

      Vol:
    E96-A No:5
      Page(s):
    963-970

    In modern cryptographic systems, physical unclonable functions (PUFs) are efficient mechanisms for many security applications, which extract intrinsic random physical variations to generate secret keys. The classical PUFs mainly exhibit static challenge-response behaviors and generate static keys, while many practical cryptographic systems need reconfigurable PUFs which allow dynamic keys derived from the same circuit. In this paper, the concept of reconfigurable multi-port PUFs (RM-PUFs) is proposed. RM-PUFs not only allow updating the keys without physically replacement, but also generate multiple keys from different ports in one clock cycle. A practical RM-PUFs construction is designed based on asynchronous clock and fabricated in TSMC low-power 65 nm CMOS process. The area of test chip is 1.1 mm2, and the maximum clock frequency is 0.8 GHz at 1.2 V. The average power consumption is 27.6 mW at 27. Finally, test results show that the RM-PUFs generate four reconfigurable 128-bit secret keys, and the keys are secure and reliable over a range of environmental variations such as supply voltage and temperature.

  • Eager Memory Management for In-Memory Data Analytics

    Hakbeom JANG  Jonghyun BAE  Tae Jun HAM  Jae W. LEE  

     
    LETTER-Computer System

      Pubricized:
    2018/12/11
      Vol:
    E102-D No:3
      Page(s):
    632-636

    This paper introduces e-spill, an eager spill mechanism, which dynamically finds the optimal spill-threshold by monitoring the GC time at runtime and thereby prevent expensive GC overhead. Our e-spill adopts a slow-start model to gradually increase the spill-threshold until it reaches the optimal point without substantial GCs. We prototype e-spill as an extension to Spark and evaluate it using six workloads on three different parallel platforms. Our evaluations show that e-spill improves performance by up to 3.80× and saves the cost of cluster operation on Amazon EC2 cloud by up to 51% over the baseline system following Spark Tuning Guidelines.

  • Executable Code Recognition in Network Flows Using Instruction Transition Probabilities

    Ikkyun KIM  Koohong KANG  Yangseo CHOI  Daewon KIM  Jintae OH  Jongsoo JANG  Kijun HAN  

     
    LETTER-Application Information Security

      Vol:
    E91-D No:7
      Page(s):
    2076-2078

    The ability to recognize quickly inside network flows to be executable is prerequisite for malware detection. For this purpose, we introduce an instruction transition probability matrix (ITPX) which is comprised of the IA-32 instruction sets and reveals the characteristics of executable code's instruction transition patterns. And then, we propose a simple algorithm to detect executable code inside network flows using a reference ITPX which is learned from the known Windows Portable Executable files. We have tested the algorithm with more than thousands of executable and non-executable codes. The results show that it is very promising enough to use in real world.

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